发明名称 METHOD FOR VERIFYING FAULT-ANALYZING FUNCTION OF SVP
摘要 PURPOSE:To verify the fault analyzing function without waiting for the corresponding between a scan-in address for generating a dummy fault and a fault correct answer value as to the method which verifies the fault analyzing function of the SVP from trace information of a fault analysis detected by the hardware. CONSTITUTION:A host 1 executes a program, the dummy fault is put in by scanning-in operation from the SVP 2 according to an indication from the host 1, and fault information (latch numbers of fault propagation destinations from a fault source latch number and their quantity) is gathered by the SVP 2; and the latch at the fault source is traced from the gathered fault information based on the analytic dictionary 22 wherein the propagation paths of respective fault latches are previously registered to judges that the fault analyzing function of the SVP 2 is normal when fault information is fault trace and when fault information less than fault trace, or output an error message as a deficiently of generated information in the analytic dictionary 22 if an analysis of the fault is completed without tracking all the gathered fault information in case of a deficiency in analytic information in the analytic dictionary 22.
申请公布号 JPH06348531(A) 申请公布日期 1994.12.22
申请号 JP19930130919 申请日期 1993.06.02
申请人 FUJITSU LTD 发明人 IGA SACHIHIRO
分类号 G06F11/22 主分类号 G06F11/22
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