发明名称 |
DATA PIPELINE DEVICE AND DATA ENCODING METHOD |
摘要 |
<p>PURPOSE: To prevent the operation delay of a certain processing stage from stopping all pipeline operations in a pipeline processing structure of a multistage constitution. CONSTITUTION: A pipeline structure processes data at continuous stages. The stages which are adjacent to each other are connected together via the valid lines (IN-VALID, OUT-VALID) and acceptance lines (IN-ACCEPT, OUT- ACCEPT). The transfer of input data are performed all at once among all stages that satisfy the conditions in every cycle period of a clock signal and only when the signals received from the following stages are affirmative. A decoding circuit is provided on one of processing stages, and the data included in a block are processed at the processing stage when one or more prescribed bit patterns are decoded at the beginning of the block.</p> |
申请公布号 |
JPH06348492(A) |
申请公布日期 |
1994.12.22 |
申请号 |
JP19930162051 |
申请日期 |
1993.06.30 |
申请人 |
PIONEER DIGITAL DESIGN CENTER LTD |
发明人 |
EIDORIAN FUIRITSUPU WAIZU;UIRIAMU FUIRITSUPU ROBINZU;MAATEIN UIRIAMU SAZURAN |
分类号 |
G06F9/38;G06F9/44;G06F15/00;G06F15/16;G06F15/80;G06F15/82;H04L23/00;H04N7/26;H04N7/50;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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