| 摘要 |
<p>PURPOSE:To simplify the circuitry of multiple sense amplifiers while realizing the conventional random access and high speed reading mode and to reduce the total chip area of the sense amplifiers and power consumption thereof. CONSTITUTION:Data lines DL0-DLn are connected with first sense amplifier circuits 1SA0-1SAn, respectively, and with a second sense amplifier circuit 2SA through transistors QPA0-QPAn. Outputs of the second sense amplifier circuit 2SA and the first sense amplifier circuits 1SA0-1SAn are connected with an output buffer circuit OB through transistors QPB-1 and QPB0-QPBn. The data lines DL0-DLn are connected, respectively, with the first sense amplifiers 1SA0-1 SAn which are connected through switch circuits SW0-SWn with the second sense amplifier circuit 2SA.</p> |
