发明名称 METHOD ENHANCING PLANARIZATION ETCHBACK MARGIN, RELIABILITY, AND STABILITY OF A SEMICONDUCTOR DEVICE
摘要 <p>Void-free planarization of sub-micron semiconductor devices results from depositing a layer of silicon-enriched oxide (210) over a conventionally fabricated device and its metal traces (200). Conventional layers of TEOS-based oxide (220) and SOG (230) are then applied over the layer of the silicon-enriched oxide (210). The silicon-enriched oxide has an index of refraction of at least 1.50, a dangling bond density of about 1017/cm3, and is about 1000 to 2000 angstroms thick. Because it is relatively deficient in oxygen atoms, the silicon-enriched oxide releases few oxygen atoms when exposed by the etching process and does not greatly accelerate the SOG etch rate. The silicon-enriched oxide has an etch rate that is only about 75 % that of the stoichiometric TEOS-based oxide and it thereby acts as a buffer that slows the etch-back process as the etching approaches the metal traces, thereby protecting the metal traces against exposure. The silicon-enriched oxide promotes stability and reliability of the underlying device by performing a shield-like function in neutralizing charges that could influence the underlying device.</p>
申请公布号 WO1994029899(A1) 申请公布日期 1994.12.22
申请号 US1994005628 申请日期 1994.05.19
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