发明名称 LATCH CIRCUIT
摘要 PURPOSE:To enable to store the data stably, by using the D type MOS transistor for the part of the feedback transfer gate and by connecting the gate to the output terminal of feedback inverter. CONSTITUTION:In the latch circuit using the MOS transistors TrQ1 to Q6 and constituted with the main inverter 1, feedback inverter 2, data input transfer gate 3 and feedback transfer gate 4, as the gate 4, D type MOS TrQ6 is used and the gate is connected to the output terminal of the inverter 2. Further, when G1(gate 3) =0 and the point A is 1 and point B is 0, or the point A is 0 and point B is 1, curretnt flows through TrQ6 to TrQ4 or through TrQ6 from TrQ3 respectively, but since the saturation current of TrQ6 is greater than the leakage current of TrQ5, if the saturation current of TrQ3 is greater than the leakage current of TrQ6, the point B holds the potential.
申请公布号 JPS54159154(A) 申请公布日期 1979.12.15
申请号 JP19780068426 申请日期 1978.06.07
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 KOIKE HIDEJI
分类号 H03K3/356 主分类号 H03K3/356
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