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发明名称
DESIGN METHOD FOR SYNCHRONOUS LOGIC CIRCUIT
摘要
申请公布号
JPH06348778(A)
申请公布日期
1994.12.22
申请号
JP19930331689
申请日期
1993.12.27
申请人
NEC CORP
发明人
SURIMATSUTO TEI CHIYATSUKURAHAA
分类号
G06F17/50;(IPC1-7):G06F15/60
主分类号
G06F17/50
代理机构
代理人
主权项
地址
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