Verfahren zur Ermittlung von Verdrängungs-Misses bei einem von einer Reihenfolge von Programmteilen gebildeten Programm,申请号DE19924206569-传众专利搜索

发明名称	Verfahren zur Ermittlung von Verdrängungs-Misses bei einem von einer Reihenfolge von Programmteilen gebildeten Programm
摘要	The cache memory is located between a main memory and the processor and serves to provide high speed operation data transfers. The collision miss determination involves transporting data between the units in the form of cache blocks of 4 to 128 bytes. A facility determines the number of misses that occur in terms of programme modules that are overwritten within the memory. The process is based upon a trace procedure in which the address reference of the programme module is determined. This identifies how often two programme sections in the cache memory overlap and the amt. of overlap. ADVANTAGE - Identifies number of collisions, between overlapping cache blocks.
申请公布号	DE4206569(C2)	申请公布日期	1994.12.22
申请号	DE19924206569	申请日期	1992.03.02
申请人	SIEMENS AG, 80333 MUENCHEN, DE	发明人	LINDMEIER, HORST, DIPL.ING., 8000 MUENCHEN, DE;HAFER, CHRISTIAN, DIPL.-ING., 8000 MUENCHEN, DE;PLANKL, JOSEF, DIPL.-INFORM., 8011 SIEGERTSBRUNN, DE;GOESMANN, KLAUS, DIPL.-PHYS., 8000 MUENCHEN, DE;WESTERHOLZ, KARL, DIPL.-ING., 8000 MUENCHEN, DE
分类号	G06F11/34;G06F12/08;G06F12/12;(IPC1-7):G06F9/445	主分类号	G06F11/34
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