| 摘要 |
The circuit provides the frame detector which is necessary for demultiplexing the received multiplexing signal sequence with the unit of channel in the receiving circuit of the communication system where the signal modulated by DM mode is multiplexed by time division multiplexing mode and is communicated. The circuit includes a D flip flop (31) reshaping the 1024 kbps multiplexing signal sequence with 1024 KHz clock input signal, a MLS detector (32) detecting the frame alignment signal of 15 bit length, an up/down counter (34) finding the correct frame channel from the MLS detector output, synchronizing a detection display block (36), deciding the acquisition or the existence of loss of the synchronous signal with the up/down counter output, and a frame clock generator (35) dividing the 1024 KHz clock and generating the 32 KHz clock synchronized with frame channel.
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