| 摘要 |
PURPOSE:To allow accurate read out of data from a memory cell even if the layout area of a DRAM is decreased or the memory capacity thereof is increased. CONSTITUTION:A plurality of pairs of sub-bit line BLs and /BLs are arranged for a pair of relatively long main bit lines BLm and /BLm. The sub-bit line BLs or /BLs is connected with the main bit line BLm or /BLm through a transfer gate T or /T. The parasitic capacitance of the pair of main bit lines BLm and /BLm per unit length is set one fourth or less that of the pair of sub-bit line. |
