| 摘要 |
PURPOSE:To obtain a stably action memory necessary to substantially reduced power consumption by dividing a memory cell array to plural parts and by operating selectively plural blocks by putting the divided memory cell array and a sense amplifier, a row decoder and a column decoder, which are connected to the memory cell array, into one block. CONSTITUTION:A memory array is divided into two blocks, and with respect to a signal to drive it, it has gate circuits G1-G4, Ga0-Gan, G1'-G4', and Ga0'- Gan' and an internal address signal generating address buffer 10i to control these gate circuits. Said gate circuits are controlled by a pair of internal address signals a1 and a1' which are outputted earlier than other address signals by the address buffer circuit 10i. In correspondence to the status of the signals a1 and a1', either group of the gate circuits G1-G4 and Ga0-Gan where the a1 signal is inputted or that of the gate circuits G1' and Ga0'-Gan' where the a1' signal is inputtted will be on or off condition. |
