| 摘要 |
A multiprocessor computer system includes main memories and processors which are connected through a crossbar switching network, and a tag copying mechanism having copies of tags of caches of the processors connected to each main memory. When each of the main memories is updated, a corresponding tag copy is checked to discriminate whether or not an updating request hits the cache having an original tag. Upon detection of a hit, a cancel or invalidate request is sent to the processor which corresponds to the hit cache, and which is not a main memory updating request source, thereby invalidating the corresponding cache line of the cache of that processor.
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