发明名称 Communications circuit having an interface for external address decoding
摘要 An adapter circuit for a local area network is disclosed, which contains logic external to the protocol handler for address comparison. The adapter uses random-access memory to store the data fields arriving after the address fields in the serial input data stream during such time as the adapter is comparing the address fields to its own address. The portion of memory used for the data storage is overwritten (recovered) by the next frame of data if the particular adapter was not addressed by the prior frame; the portion of memory used for the data storage is not overwritten if the data was addressed to the adapter. The protocol handler circuit performs an address comprising internally thereto, for intra-ring communication, and controls the recovery of the memory dependent upon the results of the comparison. The external logic performs an address comparison, primarily in inter-ring communication. An interface is provided within the protocol handler circuit to disable the recovery of the memory in the event of a true comparison found by the external logic, regardless of the results of the comparison performed by the protocol handler circuit itself. Two bi-directional signal lines are used for communication between the protocol handler circuit and the external logic. The protocol handler circuit sets a logic state on both lines to indicate the beginning of a frame, and one line or the other is set by the external logic to communicate its results.
申请公布号 US5374926(A) 申请公布日期 1994.12.20
申请号 US19930145040 申请日期 1993.10.27
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 SZCZEPANEK, ANDRE
分类号 H04L12/46;(IPC1-7):H04Q1/00 主分类号 H04L12/46
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