| 摘要 |
A method and device for performing logic functions. A logic array (1) is controlled by a plurality of DRAM cells (101). The DRAM cells are, in preferred embodiments, loaded in a serial fashion with a shift register (1205). Refresh according to one aspect of the invention utilizes a shift register (1201) with a circulating "0." A charge pump circuit, voltage boost circuit, and a variety of memory cell/logic array configurations are also disclosed.
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