Arithmetical unit including accumulating operation

摘要

An improved M-bit accumulator for increasing speed and reducing circuit size includes an N-bit (N<M) adder, a first latch having an input coupled to the output of the adder and an output coupled to an input of the adder for latching the adder output when a first clock signal is asserted, an (M-N) bit incrementer, a second latch having an input coupled to the output of the incrementer and an output coupled to the input of the incrementer for latching the incrementer output when a second clock signal is asserted, and a clock generating circuit for asserting the second clock signal in synchronism with the first clock signal only when a carry signal is generated by the adder.