Transition detection circuit

摘要

A circuit for detecting the transition of the state of logic signals at a plurality of input terminals is provided. The circuit has a transition detecting block connected to each input terminal which generates a pulse at the transition of a logic signal at the input terminal, an OR logic block connected to each transition detecting block for generating a combined logic signal from the transition detecting blocks, and a latch having SET and RESET input nodes and an output node. The SET input node is connected to the OR logic block so that the output node switches into a first logic state from a second logic state responsive to the combined logic signal on the SET input node. The circuit also has a delay unit connected to the OR logic block and to the RESET input node of the latch which precisely delays the combined logic signal to the RESET input node so that the output node of the latch switches back to the second logic state. A pulse is thus generated at the output node responsive to logic signal transitions at the input terminals. The pulse has a width controlled by the delay unit.