Level conversion circuit.

摘要

A level conversion circuit converting a digital input signal varying between first (VSS) and second (VDD1) voltage levels to a digital output signal varying between the first (VSS) and a third voltage level (VDD2) is disclosed. It includes between first (VDD2) and second (VSS) poles of a DC supply source the series connection of a load impedance (P2/P3/N3) and the main paths of a first transistor (N2) and of a second transistor (N1), to the control electrode of which the input signal is applied. The first and second transistor are of a same first conductivity type. A third transistor (P1) of a second conductivity type is connected in parallel with the second transistor (N1). The control electrode of the third (P1) and first (N2) transistors are biased by a constant DC bias voltage (VBIAS1A/VBIAS1B), and the junction point of the load impedance (P2/P3/N3) and the series connection constitutes an output terminal (OUT) of the level conversion circuit. <IMAGE>