| 摘要 |
A nonvolatile semiconductor memory system including a memory cell array (1) having a plurality of floating gate memory cell transistors (MC) arranged in a matrix of rows and columns with plurality of bit lines (BL) connected to the drains of the floating gate memory cell transistors arranged in a same column and a plurality of word lines (WL) connected to the control gates of the floating gate memory cell transistors in a same row, and a refresh circuit for periodically refreshing the stored data in the floating gate memory cell transistor.
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