| 摘要 |
<p>In a sub-micron line width process, a first layer of polysilicon (13) is patterned into lines (1, 2) spaced a predetermined distance. An oxide layer (11) is deposited. A second layer of polysilicon (14) is deposited on the insulating layer. A gate contact (19) or emitter contact (35) is formed from the second polysilicon layer (14). The gate (19) or emitter (35) is spaced from the lines (1, 2) a distance approximately equal to the thickness of the second polysilicon layer (14).</p> |
