| 摘要 |
PURPOSE:To correctly hold synchronization by turning the even cycle mutual correlation cycle value between a synchronizing code and all codes included in the plural orthogonal codes excluding the synchronizing code to zero in a code synchronizing point and within at least two chips around the point. CONSTITUTION:A memory 101 outputs the address data specified by an address bus to a databus. So as to use plural spreading codes, the symbol of each channel is made correspond to each data bus output and is stored in order from the address zero of the memory 101 according to the time series. At the time of communication, each output of a counter 102 which operates at the chip speed is connected to the address bus of the memory 101 and the plural spreading signals are outputted from the address of the memory 101. The code division multiplex is performed by the combination of the orthogonal code and the code is synchronized by the output of a reception correlator. Thus, the self correlation peak of the synchronization channel is clearly appeared near in the vicinity of the synchronization point after the synchronization is captured and the synchronization holding and later can be performed. |
