发明名称 Process and arrangement for the Boolean realization of adaline-type neural networks
摘要 PCT No. PCT/EP91/01641 Sec. 371 Date Mar. 4, 1993 Sec. 102(e) Date Mar. 4, 1993 PCT Filed Aug. 29, 1991 PCT Pub. No. WO92/04687 PCT Pub. Date Mar. 19, 1992.A process is stated with which ADALINE-type neural networks whose inputs are Boolean variables can be realized using Boolean functions. In addition, a purely digital circuit arrangement for realizing ADALINE-type neural networks is stated. The digital circuit arrangement can be constructed with the aid of a digital base circuit. The digital base circuit generates the set of Boolean functions which replaces a neuron for any value of its input weighting factors. A process for training the circuit arrangement is stated. It is thus possible to realize and to train ADALINE-type neural networks entirely with the aid of purely digital circuit arrangements.
申请公布号 US5371413(A) 申请公布日期 1994.12.06
申请号 US19930983531 申请日期 1993.03.04
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 STROBACH, PETER
分类号 G06N3/063;(IPC1-7):G06F15/18 主分类号 G06N3/063
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