发明名称 NON-VOLATILE SEMICONDUCTOR MEMORY
摘要 <p>PURPOSE:To relieve the voltage stress during the data erasing time in a flash EEPROM for contributing to the miniaturization of element and the performance enhancement. CONSTITUTION:A memory cell MC is formed in a P-type semiconductor substrate 200. A peripheral transistor TR(P) is formed in an N-type well 203 while another peripheral TR(N) is formed in a P-type well 204. The P-type well 204 is formed in another N-type well 205 to be electrically disconnected from the substrate 200. The substrate 200 e.g. metal backed is to set up the substrate potential Vsub at specific value corresponding to erasing, writing-in and reading out of data.</p>
申请公布号 JPH06338617(A) 申请公布日期 1994.12.06
申请号 JP19930126588 申请日期 1993.05.28
申请人 TOSHIBA CORP 发明人 ATSUMI SHIGERU;TANAKA SUMIO
分类号 H01L21/8247;G11C16/08;G11C16/30;H01L27/105;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L29/788 主分类号 H01L21/8247
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