发明名称 |
Bit line sensing control circuit for a semiconductor memory device |
摘要 |
A bit-line sensing control circuit includes a first circuit for activating a word line and a bit line associated with a first block of a memory cell array in response to a first initial activating clock. A delay circuit generates a second initial activating clock from the first initial activating clock a predetermined period after the first initial activation clock. A second circuit for activating a word line and a bit line associated with a second block of the memory cell array is initiated in response to the second initial activating clock. Because the second block of memory cells are sensed after the first block of memory cells, spike noise related problems are substantially avoided.
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申请公布号 |
US5371715(A) |
申请公布日期 |
1994.12.06 |
申请号 |
US19930065390 |
申请日期 |
1993.05.20 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM, MYUNG-HO |
分类号 |
G11C11/409;G11C7/22;G11C8/18;G11C11/401;G11C11/4076;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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