| 摘要 |
PURPOSE:To provide the PLL circuit which compares the phases of clock signals without dividing the frequency of an input clock signal and reduces a stationary phase error. CONSTITUTION:The internal clock signal 15 outputted from a VCO 11 is inputted to a pattern generator 12. The pattern generator 12 has a memory stored with output pattern information internally and converts the internal clock signal 15 into a clock signal 14 of the same frequency with the input clock signal 10. A phase comparator 13 receives the input clock signal 10 and clock signal 14 and compares their phases. Therefore, this PLL circuit compares the phases without dividing the frequency of the input clock signal, so the stationary phase error is reducible. |
