发明名称 METHOD AND EQUIPMENT FOR GENERATING INSPECTION SEQUENCE
摘要 PURPOSE:To generate an inspection sequence ensuring high fault coverage in the fault propagation processing of one time frame by allocating a logical value of test mode to the mode setting signal line of a scan memory element and starting the fault propagation from an allocated state. CONSTITUTION:Current time is set at T and a decision tree is allocated to a signal line M thus setting a logical value 1. A D frontier is then set for the signal line M and a logical value 0 is set for signal lines C, E in order to propagate a target fault on a signal line Y. The time is set at T-1 and a logic value 1 is set for the signal line M. Subsequently, a target pseudo-external output is set for the input signal line of a DFF 2103, the D frontier is set for the output line from the DFF 2102, and logical O is set for the input signal line to the DFF 2104 and a signal line A. The time is then set at T-2 and a logical 1 is set for the signal line M. The scan input signal to the DFF 2102 is employed as a target pseudo-external input and the D frontier arrives at a target fault thus succeeding in the fault propagation. Subsequently, the state is validated thus succeeding in the generation of inspection sequence.
申请公布号 JPH06331703(A) 申请公布日期 1994.12.02
申请号 JP19930123733 申请日期 1993.05.26
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAWAGUCHI KENICHI;HOSOKAWA TOSHINORI;MOTOHARA AKIRA
分类号 G01R31/28;G01R31/3183;G06F11/22;G06F17/50 主分类号 G01R31/28
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