| 摘要 |
<p>PURPOSE:To prevent the generation of malfunction and the useless prolongation of a waiting time by outputting a status polling signal and informing the outside that the inside is under reset operation or the reset operation is completed. CONSTITUTION:This memory device is provided with a control circuit 1 and the control circuit 1 controls an I/O buffer 2 and a command register 3 based on the control signals: the inverse of CE, the inverse of OE and the inverse of WE. When external resetting action is imparted to the memory during the mode operation, a user knows whether the inside of the memory is in a 'Ready' state or a 'Busy' state by means of a status polling signal. Consequently, the generation of malfunction and the useless prolongation of the waiting time are prevented as much as possible.</p> |
