Microcomputer

摘要

A control circuit which enables the main CPU (23) to access a memory space of the sub-CPU (1) using the test mode control register (4) is provided. The test mode control register (4) can be controlled using the main CPU bus (10). A control circuit is also provided, to jump into an abort routine by comparing the value of the program counter (5) of the sub-CPU (1) and the value in the abort vector register (7). Another control circuit is provided, to make it possible to reset the sub-CPU (1), to jump according to a test vector and to execute an abort jump under the control of the main CPU (23). It is thus simple to house the sub-CPU (1) on one chip in the traditional single-CPU construction. Thus a test environment and a debugger environment for the sub-CPU (1) are provided in the microcomputer, which has several CPUs on a single chip, without connecting the exclusive test connection of the sub-CPU (1) or the sub-CPU bus (28) to the exterior.