| 摘要 |
<p>The present invention relates to a processor architecture for executing a current task from a plurality of possible tasks. The architecture comprises: a plurality of instruction pointers (IP) associated respectively with the possible tasks and each containing the address of the current instruction to be executed of the associated task, one only of these pointers being capable of being enabled at a time in order to supply its contents as address to the memory; a priority level decoder (18) assigning a predetermined priority level to each enquiry signal and enabling the instruction pointer associated with the active enquiry signal of highest priority level; and means (20) for incrementing the contents of the enabled instruction pointer and for reinitialising it at the start address of the associated program when its contents reach the finish address of the associated program. <IMAGE></p> |
