| 摘要 |
<p>PURPOSE:To vary the ratio of cache memory command and area for data. CONSTITUTION:Over one write circuits and over one read circuits respectively corresponding to the memory areas for commands and data are provided, a memory cell array 11 are divided into blocks by dividing a data line, and divided data lines 18 and 19 are connected so as to be disconnected by switch means Tr 5 and Tr 6. Further, respective X address decoders 12 and 13 for instruction and data are divided into blocks corresponding to the division of the data line. A word line 20 of each block can be accessed by an output from both of the X address decoders for command and data. Since the respective blocks are arbitrarily combined under the control of the switch means, the respective blocks are programmed in either of the memory areas for command and data, and the dividing ratio of the memory areas for command and data is varied.</p> |
