| 摘要 |
PURPOSE:To reproduce a clock which is not errorneously locked and has less deviation even if data speed change. CONSTITUTION:A leading signal, an in-phase signal or a lagging signal are outputted from a phase comparator 12 in accordance with the comparison of the phase of an input data edge with the phase of a reproduced clock pulse. The count value of the leading signal in a counter 64 is compared with the count value of the lagging signal in a counter 66 at a comparator 68. When the former is larger, the count value of an up/down counter with code 70 is counted down. When it is smaller, the count value is counted up. The code of the count value of the up/down counter with code 70 is given to a frequency dividing ratio variable counter 38, the absolute value of the count value is modulo-added in a modulo adder 76 and a carry signal is given to the frequency dividing ratio variable counter 38 from a comparator 82. The frequency dividing ratio variable counter 38 outputs the reproduced clock pulse based on the leading signal, the in-phase signal, the lagging signal, a U/D code and the carry signal. |
