发明名称 PICTURE ENCODING AND DECODING DEVICE
摘要 PURPOSE:To reduce the production cost and to optimize the compressed code encoding processing by making divided data signals stored in memories classified by systems into blocks and multiplexing compressed data signals to generate a transmission data signal. CONSTITUTION:The picture data signal inputted to a distributing circuit 1 is distributed to memories 3a, 3b, and 3c in the unit of horizontal length of a sub-block by the command of a data distribution control circuit 2. Signals are re-arranged by address control signals from HDTV address control circuits 5a, 5b, and 5c and are read out at every picture block. The picture block signal outputted from the memory 3a is inputted to a compressing circuit 4a and is compressed and encoded to generate a compressed data signal. A multiplexing circuit 8 multiplexs compressed data signals outputted from compressing circuits in accordance with a multiplexing control circuit 9 to generate the transmission data signal. Memories are provided with the picture data signal blocking function in this manner to not only reduce a production cost but also makes the optimum compressed code encoding processing compatible.
申请公布号 JPH06326994(A) 申请公布日期 1994.11.25
申请号 JP19930115975 申请日期 1993.05.18
申请人 HITACHI LTD 发明人 OKU MASUO;TSUBOI YUKITOSHI;TAKAHASHI SUSUMU;FUJII YUKIO;ICHIGE KENJI;TSUKIJI NOBUYOSHI
分类号 H04N19/60;G06T9/00;H04N19/124;H04N19/134;H04N19/146;H04N19/42;H04N19/423;H04N19/436;H04N19/625;H04N19/88;H04N19/91;(IPC1-7):H04N7/133;G06F15/66 主分类号 H04N19/60
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