| 摘要 |
PURPOSE:To simplify a circuit constitution, and to shorten an arithmetic time at the time of multiplying a syndrome polynomial and an error position polynomial by an eraser location polynomial. CONSTITUTION:Each coefficient of the dividend polynomial of the syndrome polynomial and the error position polynomial is selected by selectors S0-S2t-1 only at the time of initialization, and multiplied by the eraser location. When an eraser location alpha<a> is inputted, the 0-order coefficient of the dividend polynomial is selected by the selector S0. multiplied by the eraser location alpha<a> by a multiplying circuit M0, and latched by a register R10. The other order coefficients of the dividend polynomial are selected by the selectors S1-S2t-1, and multiplied by the eraser locations alpha<a> by multiplying circuits M11-M12t-1. At the time of a period except initialization, registers R10-R12t-1 of the same order are selected by the selectors S0-S2t-1, and the similar arithmetic operation with the eraser locations is repeated. Then, when the entire eraser locations are inputted. each coefficient multiplied by the eraser location polynomial is obtained from an eraser location polynomial arithmetic output 14. |
