发明名称 MEMORY DEVICE FOR ARITHMETIC OPERATION
摘要 PURPOSE:To provide a memory device for arithmetic operation capable of shortening operating time, suppressing the man-hour of design, and reducing the capacity of hardware. CONSTITUTION:This device includes a write register 3 which preserves write data transiently, an address register 4 which preserves the address of the write register 3 transiently, and a means 1 which performs the readout operation and write operation of the register simultaneously by using the address of the write register 3 stored in the address register 4 and write data stored in the write register 3, and selects the register, and superimposes the operating time to read out data on that to write the data.
申请公布号 JPH06324862(A) 申请公布日期 1994.11.25
申请号 JP19930109114 申请日期 1993.05.11
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 YOSHIDA MASAHARU;TAKEUCHI IKUO;TENKAI RYOJI;YAMAZAKI KENICHI
分类号 G06F7/00;G06F9/34 主分类号 G06F7/00
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