Selbsttesteinrichtung für Speicheranordnungen, Decoder od. dgl.

摘要

PCT No. PCT/DE94/00521 Sec. 371 Date Jan. 20, 1995 Sec. 102(e) Date Jan. 20, 1995 PCT Filed May 6, 1994 PCT Pub. No. WO94/28555 PCT Pub. Date Dec. 8, 1994A self-test device for memory arrangements, decoders or the like for use during on-line operation, the word lines and/or the column lines of a memory matrix being connected to a check matrix. An error detector which generates an error signal if more than one line is activated simultaneously is connected to the check matrix. Since multiple word lines or column lines are activated in the decoder for most errors which occur, a simple self-test can be performed during on-line operation by this check matrix which can be implemented in a relatively simple and cost-effective manner.