Method for producing an earthed bit line arrangement of storage cells

摘要

The invention relates to a method for producing an earthed bit line arrangement of storage cells having the following steps: an arrangement of essentially electrically insulated, conductive word lines is arranged on a semiconductor wafer, the conductive parts of adjacent word lines being separated from each other at a specified distance, active regions are provided beside the word lines, which active regions define an arrangement of storage-cell FETs, the active regions being defined by a first active region for electrical connection to the storage-cell capacitor and a second active region for electrical connection to a bit line, a layer of a first material is applied to a specified thickness on the wafer, the layer of first material is patterned and etched, in order to form a pattern of earthed bit-line grooves for constructing earthed bit lines, bit-line contact openings for connection to the second active regions are provided in the grooves, a layer of conductively doped polysilicon is applied to a specified thickness on the wafer, in order to seal the bases of the bit-line grooves and to make electrical contact with the second active regions, in order at least partially to form bit lines, a conductive material having a higher conductivity than the conductively doped polysilicon is introduced into the bit-line grooves over the polysilicon in the grooves, an insulating material is ... on to the conductive material... Original abstract incomplete.