| 摘要 |
The cache memory unit and its control method is arranged that data bus width of system bus is equal to data width of internal cache memory and supports high speed data transfers. Cache memory unit comprises a cache unit (140) consisting of a plurality of independent memory banks; an address generator (30) generating successively addresses of a block; a data latch (40) storing temporarily a block of data. Control method comprises cache write hit, write miss, read hit, half read hit, read miss procedures.
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