发明名称 |
Semiconductor device with complementary transistors |
摘要 |
Disclosed is a system with at least two complementary transistors, having n and p channels but comprising a heterostructure of junctions between III-V group materials. In order to balance the threshold voltages in the two channels, namely the n (2DEG) and p (2DHG) channels, at least two p and n delta doped layers are included in two layers of the heterostructure, at levels included between the channels (2DEG, 2DHG) and the gate electrodes. The n delta doped layer is then removed by localized etching right above the p channel transistor. Application to fast logic circuits.
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申请公布号 |
US5367183(A) |
申请公布日期 |
1994.11.22 |
申请号 |
US19930043553 |
申请日期 |
1993.04.07 |
申请人 |
THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES |
发明人 |
PEREA, ERNESTO;DELAGEBEAUDEUF, DANIEL |
分类号 |
H01L21/8232;H01L27/06;H01L27/095;H01L29/36;H01L29/778;(IPC1-7):H01L29/80;H01L29/205 |
主分类号 |
H01L21/8232 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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