Serial data communication interface architecture

摘要

A novel serial data communication interface architecture is provided having two modes of operation that are accessed through a chip select signal in combination with a successive approximation registers signal (SARS). Once the internal data conversion begins, the chip select signal may change to any signal state without interrupting the conversion process. Serial interface data output and SARS lines are tri-stated during conversion, while the chip select signal is high. This allows data input, data output, and SARS lines to serve other purposes during conversion. If chip select signal is high at the falling edge of SARS, converted data DO bits are then provided to an internal output register. However, DO data are not immediately routed to the output. Clocking of the output data does not resume until at the first transition to low of chip select signal after the falling edge of SARS. The next conversion is not initiated until the second transition of chip select back to low after the falling edge of SARS signaling the end of conversion.