发明名称 |
Semiconductor memory device having a back-bias voltage generator |
摘要 |
In typical MOS integrated circuit devices, the level of the back-bias voltage which is generated by a built-in back-bias generation circuit and is supplied to a semiconductor substrate is changed by an undesirable leakage current flowing through the semiconductor substrate. The leakage current is not constant. Instead, it becomes relatively small when a main circuit formed on the semiconductor substrate such as a dynamic RAM is not operative, and relatively great when such a circuit is operative. To reduce the change of the back-bias voltage resulting from the change of the leakage current, a back-bias voltage generation circuit is provided which has output capacity of a plurality of levels. Its output capacity is increased in response to an operation control signal of the main circuit. The level change of the back-bias voltage generation circuit can further be reduced by providing a level detection circuit for detecting the level change and a feedback circuit for controlling the back-bias voltage generation circuit in accordance with the output of the level detection circuit.
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申请公布号 |
USRE34797(E) |
申请公布日期 |
1994.11.22 |
申请号 |
US19920962329 |
申请日期 |
1992.10.16 |
申请人 |
HITACHI, LTD. |
发明人 |
SATO, KATSUYUKI;YANAGISAWA, KAZUMASA |
分类号 |
G11C11/407;G11C5/14;G11C11/4074;(IPC1-7):G11C7/02 |
主分类号 |
G11C11/407 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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