| 摘要 |
A finite impulse response filter (10) incorporates a two input data multiplexer (12) and a series of delay registers (18, 20, and 22) for processing input samples off an input data line (14). The data multiplexer (12) selects between a feedback sample generated at the last delay register (22) and an input sample received on the input data line (14). A multiplier (24) combines a coefficient as selected by a coefficient multiplexer (26) with the selected sample to drive an adder (28). The adder (28) sums sequential products from the multiplexer (24) to drive an accumulator register (30). The accumulator register (30) provides the adder (28) with the sum of products feedback in order that the adder (28) may sum successive products together. At the completion of a cycle, the data multiplexer (12) selects a new input sample off the input data line (14) and the adder (28) to accumulator register (30) combination is reset through a zero adjust generator (32).
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