Tag initialization in a controller for two-way set associative cache

摘要

A cache controller tag ram is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The two ways, a right way and a left way, each store tag addresses. First means are provided for asserting a flush signal upon the condition that a warm start reset is recognized or a power up condition is recognized. Logic causes all pending write requests to be withdrawn in response to the flush signal. The directory is cleared by setting all valid, write protect and least recently used (LRU) bits to zero in both of the ways. Subsequent write requests use a line fill algorithm to ensure that correct data is written into the directory by choosing which way to select for a line fill after the bits have been cleared.