| 摘要 |
A semiconductor memory device according to the present invention includes a memory cell array, internal circuits for reading and writing of data of the memory cell array, a test mode controller, and power-on-reset circuits. The test mode controller sets a test mode of the memory cell array in response to a predetermined pattern of change of logic levels of at least several control signals out of a plurality of control signals for controlling the internal circuits. The power-on-reset circuits set the test mode controller in an initial state over a variable period which is defined based on a timing of change of a logic level of a control signal determining a timing of setting of the test mode out of the at least several control signals, in response to power-on. As a result, it is possible to prevent the semiconductor memory device from erroneously entering the test mode caused by a noise or the like after power-on. |
