| 摘要 |
PURPOSE: To perform test on an integrated logic circuit with no dependency upon a complicated external test pattern by making feedback to those memory elements situated farther than the one in a scan bus, and conducting a clock control. CONSTITUTION: Two of the output terminals 31 capable of being scanned if a shift register latch 32 are connected with an exclusive OR gate 35. A multiplexer 36 controlled by a test register is furnished so that the output signal of this gate can directly be fed back to the operational input end of the latch 32. With this connection, a linear feedback shift register circuit is formed. Accordingly the shift register configured with a scan pass of latch itself 32 operates as a pattern generator which applies a plurality of varying input signal 31 on the next combination logic circuit. The test can be conducted by feeding a supply voltage and a scan and a slave clock signal to the device while an accelerative lifetime test is being carried out, and the test on the device can be controlled through the register. |
