| 摘要 |
PURPOSE: To effectively reduce a parasitic capacitance and further reduce device dimensions by providing a digital electrode in continuous conductive region to connect first and second semiconductor regions and installing each electrode digit at the upper part of the second region for both semiconductor regions. CONSTITUTION: A first semiconductor region 102 and a second semiconductor region 103 are formed on a semiconductor substrate 101. Emitter digits 107 and 108 that are emitter electrodes are arranged on the second semiconductor region 103. Also, a digital electrode 109 is self-aligned to a continuous conductive region 105. The continuous conductive region 105 is arranged between the digital electrodes 109 on the second semiconductor region 103 and is electrically connected to the first semiconductor region 102 and forms a common electrode. An insulation region 106, the digital electrode 109, and a continuous conductive region 105 inserted between the emitter fingers 107 and 108 and the continuous conductive region 105 are nearly flat, thus reducing a parasitic capacitance effectively and dimensions. |
