| 摘要 |
A three-port Josephson memory cell has one input port (a data line) and two output ports (first and second sense lines). The memory cell receives a write enable pulse on a write line to store a bit of data from the data line as circulating supercurrent. The memory cell also receives a first read enable pulse on a first read line to enable assertion of the stored data onto the first sense line, and receives a second read enable pulse on a second read line to enable assertion of the stored data onto the second sense line. To provide non-destructive readout and wide margins, the memory cell includes a write gate responsive to the write enable pulse for storing current from the data line, a first read gate responsive to the stored current and the first read enable pulse, a second read gate responsive to the stored current and the second read enable pulse, a first buffer gate responsive to the first read gate for asserting a data output signal on the first sense line, and a second buffer gate responsive to the second read gate for asserting a data output signal on the second sense line. In the preferred construction, the current is stored in two storage loops. One storage loop includes a control current path for the first read gate, and the other storage loop includes the control current path for the second read gate.
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