Buried bit line DRAM cell

摘要

Ions of dopant are implanted into predetermined locations in a doped semiconductor substrate in sufficient concentration to form a buried conductor regions. A thick dielectric layer overlies the surface of the doped substrate. A first polysilicon layer is formed and patterned on the silicon dioxide layer by a mask and etching to form conductor lines, covered by a dielectric. A second polysilicon layer is formed on the second dielectric layer and patterned to form a first capacitor plate. A third dielectric layer is formed on the surface of the second polysilicon layer. A third polysilicon layer is formed on the third dielectric layer and patterned to form a top capacitor plate. A layer of BPSG is deposited upon the third layer of polysilicon.