| 摘要 |
PURPOSE:To precharge couples of bit lines in the same column speedily to the same potential and to increase a readout speed by connecting a transistor (TR) for equalization between bit lines near a memory cell which is precharged latest. CONSTITUTION:The TRT3 for equalization is connected to bit lines BL and -BL near the memory cell M2 which is farthest from precharging TRs T1 and T2 and at distance from the T1 and T2. Therefore, when the lines BL and -BL are precharged, the lines BL and -BL is equalized in potential speedily by the T3 near the memory cell which is precharged latest. |
