| 摘要 |
The present invention provides a bus transceiver incorporating a high speed, binary transfer mode for the half-duplex transfer of data signals with a ternary control transfer mode having a full duplex dominant logic transmission scheme for the full duplex transfer of control signals. In one embodiment of the present invention, the above-noted transfer modes are implemented in a bus architecture which includes at least a first communications node coupled to a second communications node via a twisted pair, serial bus. Each node comprises first transceiver and second transceivers having a differential driver for driving on the bus signal states comprising first and second signal states having equal current amplitudes opposite in sign and a third signal state having approximately a zero current amplitude, a high speed binary receiver for receiving high speed data signals during data transfer phases and a ternary receiver for receiving control signals during control transfer phases. To permit the receivers of the present invention to receive the transmitted signals at the amplitude required to detect the proper bus voltage values, the present invention further provides a means for common mode shifting of the signals at the front end of the receivers while providing for a voltage offset independent of the fabrication process. This common mode shifting means also permits the implementation of a single ternary receiver in place of each of the binary, ternary and preemptive signaling receivers for each transceiver. In this manner, the present invention can be modified so that both transfer modes in addition to the preemptive signaling method can be performed using a single ternary receiver. |
