发明名称 Multi-processor computer system having process-independent communication register addressing.
摘要 <p>A computer system having a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processors having both serial and parallel code segments. During serial execution, a process is executed by a single processors, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available. However, if all processors are busy, then the processor conducting the serial operation will also execute all of the parallel operations. Thus, the processors are self-allocated, rather than being used on a demand or master-servant basis. This permits a greater throughput for the system because processors are not held idle when there is available process work to be done. &lt;IMAGE&gt;</p>
申请公布号 EP0623875(A2) 申请公布日期 1994.11.09
申请号 EP19940250185 申请日期 1989.01.25
申请人 CONVEX COMPUTER CORPORATION 发明人 CHASTAIN, DAVID M.;MANKOVICH, JAMES E.;GOSTIN, GARY B.
分类号 G06F9/44;G06F9/46;G06F9/50;G06F15/167;G06F15/173;(IPC1-7):G06F9/46 主分类号 G06F9/44
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