发明名称 Interlock arrangement for instruction dependency.
摘要 A method and system are disclosed which allow a computer program to execute properly in object code compatible processing systems which have latencies different from those with which the program was created or compiled. This resulting compatibility of the computer program is achieved because the invention protects the precedence of operations within the computer program using latency assumptions which were used when creating the computer program. When the computer program is created, latency assumption information is efficiently provided within the computer program. Thereafter, when the computer program is executed, it is able to advise the processing system of the latency assumptions with which it was created. Various ways are described in which the processing system can utilize the latency assumptions when executing the computer program so as to ensure compatibility.
申请公布号 GB2277820(A) 申请公布日期 1994.11.09
申请号 GB19940008864 申请日期 1994.05.04
申请人 * HEWLETT-PACKARD COMPANY 发明人 MICHAEL A * SCHLANSKER;B. RAMAKRISHNA * RAU;RAJIV * GUPTA;JOSEPH A. * FISHER
分类号 G06F9/38;(IPC1-7):G06F9/38;G06F9/30 主分类号 G06F9/38
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