| 摘要 |
A silicon carrier wafer (82) is thermally processed to produce a silicon dioxide layer (12) on a surface thereof. A patterned metal conductor layer (16) is formed on the silicon dioxide layer (12) using silicon processing technology which enables high resolution and density. A silicon nitride layer (14) is formed on the conductor layer (16) and exposed areas of the silicon dioxide layer (12). Vias (32, 34, 36) are formed through the silicon nitride layer (14) for ohmic contact to appropriate points of the conductor layer (16). Thick metal contact layers (38, 40, 42, 46, 48) are formed on the silicon nitride layer (14) in ohmic connection with the vias (32, 34, 36) and indium bumps (50, 52, 54) are formed on the contact layers (38, 40, 42, 44, 46, 48). The carrier (82), which serves as a support during processing is removed by etching, with the silicon dioxide layer (12) acting as an etch stop. Integrated circuit chips (18) are mounted on the silicon dioxide layer (2) and connected to the conductor pattern through openings (24, 26) formed in the silicon dioxide layer (12). A substrate (56) which has electrical circuitry (58, 60, 62, 76) and bumps (70, 72, 74) formed thereon is adhered to the silicon nitride layer (14), with the circuitry (58, 60, 62, 76) being connected to the conductor layer (16) by the bumps (50, 52, 54, 70, 72, 74). The conductor layer (16) provides power and other interconnects for the chips (18) and circuitry (58, 60, 62, 76) on the substrate (56), thereby increasing the size and density of circuit integration and improving heat dissipation. <IMAGE> |
